Introduction
ATA/IDE Overview
Host Buses
Evolution of ATA
Electrical Interface
Signal Levels and Descriptions
Termination
Functional Interface
Register Addressing
PIO Transfers & Timing
DMA Transfers & Timing
Flow Control
Higher Speed Proposals
Command Block and Control
Block Registers
This section is a detailed discussion
of the contents and use of each register
Commands and Operations
Initialization Commands
Power Control Commands
Secure Mode Commands
SMART Support
Removable Media Support
Host Services Overview
PC Compatible Memory Map
BIOS Services
Interrupts
Fixed Disk Parameter Table
INT 13h
Accessing via the BIOS
INT 13h Interface
INT 13h Command Codes |
Expansion ROM
POST Expansion Area Scanning
IDE Disk Addressing
The 528 MB Barrier
The 8GB Barrier
CHS and LBA Addressing
INT 13h Extensions
Bypassing the BIOS
ISA Bus IDE
ISA to to ATA Signal Mapping
ISA Bus PIO
ISA Bus DMA
VL Bus IDE
Why Local Bus I/O?
Typical Host Configuration
IDE on VL Bus
PCI Bus IDE
PCI Bus Basics
Dual Channel Adapter
PCI Bus PIO
PCI Bus DMA
PCI/IDE Bus Mastering
Future ATA Developments
ATA-4
New Competing Interfaces
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