INTRODUCTION TO 3D NAND (1/2 Day)


Chuck-Sobey126x152B$795
Will NAND flash continue to scale to geometries below 10nm? Innovation in semiconductor process technology has continued beyond many end-of-life predictions in the past. The most likely reason why development of 2D NAND flash would stop is the emergence of an approach with a better return-on-investment. Is 3D NAND that approach?

Samsung announced mass production of 3D NAND chips at a previous Flash Memory Summit and has been shipping SSDs containing them for the past year. New wafer fabrication factories are being built, and every NAND manufacturer has announced plans for 3D – most targeting mass production in 2015 – 2016.

How should your company position itself for the opportunities and challenges that such a fundamental technology shift will bring? Now is the time to prepare yourself, your key staff, and your company to be ready for the future. Prepare for 3D flash today!

Reliable, unbiased information is critical for making the right decisions! So don’t proceed (and spend a lot of development money) without a clear understanding of the fundamentals, opportunities, and challenges of this exciting new technology!

Learn from well-known storage industry consultant and expert instructor, Chuck Sobey, about the possibilities and challenges of 3D flash device technologies, alternative array architectures, controller partitioning, algorithm developments, and the problems posed by the technology.

This tutorial is a great way to get up-to-speed quickly on a major technology shift. Cut through the hype and confusion surrounding 3D! Conquer the fear and apprehension regarding how 3D NAND might affect you! Build a firm foundation for yourself and your team. Learn how to ask the tough questions and know when you get the right answers!

This tutorial is designed for engineers, managers, and executives who must make immediate decisions about responding to the shift to 3D technology. It is presented by KnowledgeTek, the world’s leading data storage technology training company. Suggested prerequisites include a technical background and an interest in 3D technology; the class does not assume detailed engineering knowledge of flash memory or semiconductor processing.

1. 2D NAND FLASH OVERVIEW
  • What is 3D?
  • 2D wraparound and planar floating-gate flash cells
  • The 2D NAND flash array
  • Problems and challenges with 2D flash
  • Charge trapping NAND flash
2. THE CASE FOR 3D
  • ITRS roadmap for 3D NAND
  • Layers and line widths
  • Etching vs lithography
  • Speed, power, and interconnects
  • The device determines the system
3. COMPETING TECHNOLOGIES & ARCHITECTURES FOR 3D FLASH
  • Vertical transistor designs
  • 3D array architectures
  • Accessing data
  • SLC and MLC in 3D
  • Resistive storage technologies (ReRAM)
4. PROCESS, DESIGN,& TEST CHALLENGES
  • Etch and deposition
  • Power density and thermal issues
  • Logical-to-physical translation in 3D
  • Testing, characterization, and defects
  • Controller partitioning
5. NEXT STEPS TO PREPARE FOR 3D
  • Planning your strategy
  • Creating your pilot team
  • A lesson from the Wrath of Khan
  • Suggested sources of reference information